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System-on-Chip Design and Implementation

Bibliographic Data

ID20295679
AuthorsLinda E M Brackenbury, Luis A Plana (0000-0002-6113-3929, University of Manchester), Jeffrey Pepper (University of Manchester)
Year2010
Volume53
Issue2
Pages272-281
Publication date2010-05-01
Open AccessYes
TypeARTICLE
VenueIEEE Transactions on Education (JOURNAL)
Journal identifiersISSN: 0018-9359 • E-ISSN: 1557-9638
PublisherInstitute of Electrical and Electronics Engineers (IEEE) (PUBLISHER)
DOI10.1109/te.2009.2014858
OpenAlexW2117541625
LanguageEN
Citations received2
References cited6

The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant practical work to illustrate the material taught and is centered around a single design example of a drawing machine. The exercises are composed so that students can regard themselves as part of a design team where they undertake the complete design of their own particular section of the system. These design tasks range from algorithmic specification and transaction-level modeling (TLM) of the architecture down to describing the design at the register transfer level (RTL) with subsequent verification of their prototype on a field-programmable gate array (FPGA). With this approach, students are able to explore and gain experience of the different techniques used at each level of the design hierarchy and the problems in translating to the next level down. Throughout the module, there is emphasis on using industry standard tools for the modeling and simulation, leading to the use of the SystemC and Verilog hardware description languages and Cadence for the simulation environment

Computer architecture · Electronic design automation · Electronic system-level design and verification · Embedded system · Field-programmable gate array · Hardware description language · Logic gate · Logic simulation · Logic synthesis · Register-transfer level · Software engineering · SystemC · Transaction-level modeling · Verilog · Computer Science · Embedded Systems Design Techniques · Interconnection Networks and Systems · VLSI and Analog Circuit Testing

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  • Agent-Based Simulation of Learning Dissemination in a Project-Based Learning Context Considering the Human Aspects

    Open Access•Laio Oriel Seman, Romeu Hausmann et al.•IEEE Transactions on Education•2018

  • An Undergraduate System-on-Chip (SoC) Course for Computer Engineering Students

    Open Access•A Bindal, Amit Kumar Bindal et al.•IEEE Transactions on Education•2005

Citations per year0.13
Citation span2011 - 2018 (8)
Highly citedNo

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