A P-Channel MOS IC for Educational Purposes Using a Two-Photomask Process
Bibliographic Data
| ID | 20294664 |
|---|---|
| Authors | Katsufusa Shohno (Sophia University), Kathleen J Callanan (Sophia University) |
| Year | 1977 |
| Volume | 20 |
| Issue | 2 |
| Pages | 92-97 |
| Publication date | 1977-05-01 |
| Open Access | Yes |
| Type | ARTICLE |
| Venue | IEEE Transactions on Education (JOURNAL) |
| Journal identifiers | ISSN: 0018-9359 • E-ISSN: 1557-9638 |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) (PUBLISHER) |
| DOI | 10.1109/te.1977.4321120 |
| OpenAlex | W2028333516 |
| Language | EN |
| Citations received | 2 |
| References cited | 2 |
The two-photomask process for the fabrication of p-channel MOS devices provides a full introduction to the fundamental planar process. A 1000 A double layer insulator fim of silicon dioxide (700 Å) and silicon nitride (300 Å) is used for the gate and field regions of the devices. Using chemical vapor deposited boron nitride as the boron diffusion source eliminates the usual photo-process steps for the etching of the contact holes for the source and drain. The mask alignment tolerance can be designed to be within one half of the lateral diffusion length of 8 Mm. This process can be applied to a variety of devices and can be completed by engineering students in only three seven-hour laboratory days. Single chip inverters and RS flip-flop circuits are illustrated, along with an analysis of their parasitics
Electronic engineering · Etching (microfabrication) · Fabrication · Layer (electronics) · Nanotechnology · Optoelectronics · Parasitic extraction · Photomask · Planar · Process (computing) · Resist · Silicon · Silicon on insulator · Advancements in Photolithography Techniques · Advancements in Semiconductor Devices and Circuit Design · Computer Science · Engineering · Materials Science · Semiconductor materials and devices
| Citations per year | 0.04 |
|---|---|
| Citation span | 1980 - 1986 (7) |
| Highly cited | No |