A Semicustom VLSI System Design Course Supported by the General Electric Microelectronics Center
Bibliographic Data
| ID | 20295688 |
|---|---|
| Authors | James H Aylor, Edward A Parrish (University of Virginia), Kenneth L Pocek (Institute of Microelectronics) |
| Year | 1986 |
| Volume | E-29 |
| Issue | 2 |
| Pages | 85-89 |
| Publication date | 1986-05-01 |
| Open Access | Yes |
| Type | ARTICLE |
| Venue | IEEE Transactions on Education (JOURNAL) |
| Journal identifiers | ISSN: 0018-9359 • E-ISSN: 1557-9638 |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) (PUBLISHER) |
| DOI | 10.1109/te.1986.5570605 |
| OpenAlex | W2040954569 |
| Language | EN |
| Citations received | 1 |
| References cited | 2 |
This paper presents an approach to VLSI system design and fabrication using gate arrays which has been implemented at the University of Virginia in conjunction with the General Electric Microelectronics Center (GE-MEC). Material initially developed by GE-MEC was modified and incorporated into a new graduate course to supplement that which already existed in the area of VLSI system design. A software tool set which includes functional and fault simulators for the TEGAS TM1 hardware description language, a testability analyzer, and packages for cell placement, channel routing, and system delay extraction was used for chip design. Chip fabrication of successful design projects is the responsibility of GE-MEC
Application-specific integrated circuit · Center (category theory) · Chip · Computer architecture · Computer hardware · Electrical engineering · Embedded system · Integrated circuit design · Microelectronics · Operating system · Reliability engineering · Testability · Very-large-scale integration · Computer Science · Engineering · Experimental Learning in Engineering · Integrated Circuits and Semiconductor Failure Analysis · Software · VLSI and Analog Circuit Testing
| Citations per year | 0.03 |
|---|---|
| Citation span | 1988 - 1988 (1) |
| Highly cited | No |